Exynos542x: Add workaround for ARM errata 799270

Exynos542x: Add workaround for ARM errata 799270

This patch adds workaround for the ARM errata 799270 which says
"If the L2 cache logic clock is stopped because of L2 inactivity,
setting or clearing the ACTLR.SMP bit might not be effective. The bit is
modified in the ACTLR, meaning a read of the register returns the
updated value. However the logic that uses that bit retains the previous
value."

Signed-off-by: Kimoon Kim <[email protected]>
Signed-off-by: Akshay Saraswat <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>